EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_RS232_DCE_RX_pin I 1 fpga_0_RS232_DCE_RX fpga_0_RS232_DCE_TX_pin O 1 fpga_0_RS232_DCE_TX fpga_0_LEDs_8Bit_GPIO_d_out_pin O 0:7 fpga_0_LEDs_8Bit_GPIO_d_out fpga_0_Ethernet_MAC_PHY_tx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_tx_clk fpga_0_Ethernet_MAC_PHY_rx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_clk fpga_0_Ethernet_MAC_PHY_rst_n_pin O 1 fpga_0_Ethernet_MAC_PHY_rst_n fpga_0_Ethernet_MAC_PHY_tx_data_pin O 3:0 fpga_0_Ethernet_MAC_PHY_tx_data fpga_0_Ethernet_MAC_PHY_tx_en_pin O 1 fpga_0_Ethernet_MAC_PHY_tx_en fpga_0_Ethernet_MAC_PHY_rx_data_pin I 3:0 fpga_0_Ethernet_MAC_PHY_rx_data fpga_0_Ethernet_MAC_PHY_dv_pin I 1 fpga_0_Ethernet_MAC_PHY_dv fpga_0_Ethernet_MAC_PHY_rx_er_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_er fpga_0_Ethernet_MAC_PHY_crs_pin I 1 fpga_0_Ethernet_MAC_PHY_crs fpga_0_Ethernet_MAC_PHY_col_pin I 1 fpga_0_Ethernet_MAC_PHY_col fpga_0_DDR2_SDRAM_DDR2_ODT_pin O 1 fpga_0_DDR2_SDRAM_DDR2_ODT fpga_0_DDR2_SDRAM_DDR2_Addr_pin O 12:0 fpga_0_DDR2_SDRAM_DDR2_Addr fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin O 1:0 fpga_0_DDR2_SDRAM_DDR2_BankAddr fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CAS_n fpga_0_DDR2_SDRAM_DDR2_CE_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CE fpga_0_DDR2_SDRAM_DDR2_CS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CS_n fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_RAS_n				# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_DDR2_SDRAM_DDR2_WE_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_WE_n fpga_0_DDR2_SDRAM_DDR2_Clk_pin O 1 fpga_0_DDR2_SDRAM_DDR2_Clk fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_Clk_n fpga_0_DDR2_SDRAM_DDR2_DM_pin O 1:0 fpga_0_DDR2_SDRAM_DDR2_DM fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin I 1 fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin O 1 fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O fpga_0_DDR2_SDRAM_DDR2_DQS IO 1:0 fpga_0_DDR2_SDRAM_DDR2_DQS fpga_0_DDR2_SDRAM_DDR2_DQS_n IO 1:0 fpga_0_DDR2_SDRAM_DDR2_DQS_n fpga_0_DDR2_SDRAM_DDR2_DQ IO 15:0 fpga_0_DDR2_SDRAM_DDR2_DQ fpga_0_FLASH_Mem_OEN_pin O 1 fpga_0_FLASH_Mem_OEN fpga_0_FLASH_Mem_CEN_pin O 0:0 fpga_0_FLASH_Mem_CEN fpga_0_FLASH_Mem_WEN_pin O 1 fpga_0_FLASH_Mem_WEN fpga_0_FLASH_emc_ben_gnd_pin O 1 net_vcc fpga_0_FLASH_emc_rp_pin O 1 net_vcc fpga_0_FLASH_emc_wp_pin O 1 net_vcc fpga_0_FLASH_Mem_A_pin O 10:30 fpga_0_FLASH_Mem_A fpga_0_FLASH_Mem_DQ_pin IO 0:15 fpga_0_FLASH_Mem_DQ sys_clk_pin I 1 dcm_clk_s  CLK  sys_rst_pin I 1 sys_rst_s  RESET