
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc.  All rights reserved. 
* 
* Description: Driver parameters
*
*******************************************************************/

/*
 *
 * auto-config.h - automatically generated, do not edit
 *
 * EDK Version: Xilinx EDK 10.1.03 EDK_K_SP3.6 
 */


/* MAIN_MEMORY Settings */
#define CONFIG_XILINX_ERAM_START (0x8c000000)
#define CONFIG_XILINX_ERAM_SIZE (0x04000000)

/* FLASH_MEMORY Settings */
#define CONFIG_XILINX_FLASH_START (0x88400000)
#define CONFIG_XILINX_FLASH_SIZE (0x00400000)
#define CONFIG_XILINX_FLASH_WIDTH (16)
#define CONFIG_XILINX_FLASH_DATAWIDTH_MATCHING (1)

/* LMB_MEMORY Settings */
#define CONFIG_XILINX_LMB_START (0x00000000)
#define CONFIG_XILINX_LMB_SIZE (0x00002000)

/* System Clock Frequency */
#define CONFIG_XILINX_CPU_CLOCK_FREQ (100000000)

/* Definitions for MICROBLAZE0 */
#define CONFIG_XILINX_MICROBLAZE0_INSTANCE "microblaze_0"
#define CONFIG_XILINX_MICROBLAZE0_SCO (0)
#define CONFIG_XILINX_MICROBLAZE0_DATA_SIZE (32)
#define CONFIG_XILINX_MICROBLAZE0_DYNAMIC_BUS_SIZING (1)
#define CONFIG_XILINX_MICROBLAZE0_FAMILY "spartan3a"
#define CONFIG_XILINX_MICROBLAZE0_INSTANCE "microblaze_0"
#define CONFIG_XILINX_MICROBLAZE0_AREA_OPTIMIZED (1)
#define CONFIG_XILINX_MICROBLAZE0_INTERCONNECT (1)
#define CONFIG_XILINX_MICROBLAZE0_DPLB_DWIDTH (32)
#define CONFIG_XILINX_MICROBLAZE0_DPLB_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MICROBLAZE0_DPLB_BURST_EN (0)
#define CONFIG_XILINX_MICROBLAZE0_DPLB_P2P (0)
#define CONFIG_XILINX_MICROBLAZE0_IPLB_DWIDTH (32)
#define CONFIG_XILINX_MICROBLAZE0_IPLB_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MICROBLAZE0_IPLB_BURST_EN (0)
#define CONFIG_XILINX_MICROBLAZE0_IPLB_P2P (0)
#define CONFIG_XILINX_MICROBLAZE0_D_PLB (1)
#define CONFIG_XILINX_MICROBLAZE0_D_OPB (0)
#define CONFIG_XILINX_MICROBLAZE0_D_LMB (1)
#define CONFIG_XILINX_MICROBLAZE0_I_PLB (1)
#define CONFIG_XILINX_MICROBLAZE0_I_OPB (0)
#define CONFIG_XILINX_MICROBLAZE0_I_LMB (1)
#define CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR (1)
#define CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR (1)
#define CONFIG_XILINX_MICROBLAZE0_USE_BARREL (0)
#define CONFIG_XILINX_MICROBLAZE0_USE_DIV (0)
#define CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL (1)
#define CONFIG_XILINX_MICROBLAZE0_USE_FPU (0)
#define CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS (0)
#define CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION (0)
#define CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION (0)
#define CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION (0)
#define CONFIG_XILINX_MICROBLAZE0_IPLB_BUS_EXCEPTION (0)
#define CONFIG_XILINX_MICROBLAZE0_DPLB_BUS_EXCEPTION (0)
#define CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION (0)
#define CONFIG_XILINX_MICROBLAZE0_FPU_EXCEPTION (0)
#define CONFIG_XILINX_MICROBLAZE0_FSL_EXCEPTION (0)
#define CONFIG_XILINX_MICROBLAZE0_PVR (0)
#define CONFIG_XILINX_MICROBLAZE0_PVR_USER1 (0x00000000)
#define CONFIG_XILINX_MICROBLAZE0_PVR_USER2 (0x00000000)
#define CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED (1)
#define CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PC_BRK (1)
#define CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK (0)
#define CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK (0)
#define CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE (0)
#define CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE (1)
#define CONFIG_XILINX_MICROBLAZE0_RESET_MSR (0x00000000)
#define CONFIG_XILINX_MICROBLAZE0_OPCODE_0X0_ILLEGAL (0)
#define CONFIG_XILINX_MICROBLAZE0_FSL_LINKS (0)
#define CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE (32)
#define CONFIG_XILINX_MICROBLAZE0_USE_EXTENDED_FSL_INSTR (0)
#define CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR (0x8C000000)
#define CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR (0x8FFFFFFF)
#define CONFIG_XILINX_MICROBLAZE0_USE_ICACHE (1)
#define CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR (1)
#define CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS (15)
#define CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE (2048)
#define CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL (1)
#define CONFIG_XILINX_MICROBLAZE0_ICACHE_LINE_LEN (4)
#define CONFIG_XILINX_MICROBLAZE0_ICACHE_ALWAYS_USED (0)
#define CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR (0x8C000000)
#define CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR (0x8FFFFFFF)
#define CONFIG_XILINX_MICROBLAZE0_USE_DCACHE (1)
#define CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR (1)
#define CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG (15)
#define CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE (2048)
#define CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL (1)
#define CONFIG_XILINX_MICROBLAZE0_DCACHE_LINE_LEN (4)
#define CONFIG_XILINX_MICROBLAZE0_DCACHE_ALWAYS_USED (0)
#define CONFIG_XILINX_MICROBLAZE0_USE_MMU (0)
#define CONFIG_XILINX_MICROBLAZE0_MMU_DTLB_SIZE (4)
#define CONFIG_XILINX_MICROBLAZE0_MMU_ITLB_SIZE (2)
#define CONFIG_XILINX_MICROBLAZE0_MMU_TLB_ACCESS (3)
#define CONFIG_XILINX_MICROBLAZE0_MMU_ZONES (16)
#define CONFIG_XILINX_MICROBLAZE0_USE_INTERRUPT (1)
#define CONFIG_XILINX_MICROBLAZE0_USE_EXT_BRK (1)
#define CONFIG_XILINX_MICROBLAZE0_USE_EXT_NM_BRK (1)
#define CONFIG_XILINX_MICROBLAZE0_INSTANCE "microblaze_0"
#define CONFIG_XILINX_MICROBLAZE0_HW_VER "7.10.d"

/* Definitions for LMB_BRAM_IF_CNTLR_0 */
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE "dlmb_cntlr"
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR (0x00000000)
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR (0x00001FFF)
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK (0x80000000)
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH (32)
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH (32)
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE "dlmb_cntlr"
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER "2.10.a"

/* Definitions for LMB_BRAM_IF_CNTLR_1 */
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE "ilmb_cntlr"
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR (0x00000000)
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR (0x00001FFF)
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK (0x80000000)
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH (32)
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH (32)
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE "ilmb_cntlr"
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER "2.10.a"

/* Definitions for BRAM_IF_CNTLR_0 */
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_INSTANCE "xps_bram_if_cntlr_1"
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_BASEADDR (0x86408000)
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_HIGHADDR (0x86409FFF)
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_SPLB_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_SPLB_AWIDTH (32)
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_SPLB_DWIDTH (32)
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_SPLB_NUM_MASTERS (2)
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_SPLB_MID_WIDTH (1)
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_SPLB_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_SPLB_P2P (0)
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_SPLB_SMALLEST_MASTER (32)
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_FAMILY "spartan3a"
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_INSTANCE "xps_bram_if_cntlr_1"
#define CONFIG_XILINX_BRAM_IF_CNTLR_0_HW_VER "1.00.a"

/* Definitions for UARTLITE_0 */
#define CONFIG_XILINX_UARTLITE_0_INSTANCE "RS232_DCE"
#define CONFIG_XILINX_UARTLITE_0_FAMILY "spartan3a"
#define CONFIG_XILINX_UARTLITE_0_SPLB_CLK_FREQ_HZ (62500000)
#define CONFIG_XILINX_UARTLITE_0_BASEADDR (0x84000000)
#define CONFIG_XILINX_UARTLITE_0_HIGHADDR (0x8400FFFF)
#define CONFIG_XILINX_UARTLITE_0_SPLB_AWIDTH (32)
#define CONFIG_XILINX_UARTLITE_0_SPLB_DWIDTH (32)
#define CONFIG_XILINX_UARTLITE_0_SPLB_P2P (0)
#define CONFIG_XILINX_UARTLITE_0_SPLB_MID_WIDTH (1)
#define CONFIG_XILINX_UARTLITE_0_SPLB_NUM_MASTERS (2)
#define CONFIG_XILINX_UARTLITE_0_SPLB_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_UARTLITE_0_SPLB_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_UARTLITE_0_BAUDRATE (115200)
#define CONFIG_XILINX_UARTLITE_0_DATA_BITS (8)
#define CONFIG_XILINX_UARTLITE_0_USE_PARITY (0)
#define CONFIG_XILINX_UARTLITE_0_ODD_PARITY (0)
#define CONFIG_XILINX_UARTLITE_0_INSTANCE "RS232_DCE"
#define CONFIG_XILINX_UARTLITE_0_HW_VER "1.00.a"
#define CONFIG_XILINX_UARTLITE_0_IRQ (2)

/* Definitions for MDM_0 */
#define CONFIG_XILINX_MDM_0_INSTANCE "debug_module"
#define CONFIG_XILINX_MDM_0_FAMILY "spartan3a"
#define CONFIG_XILINX_MDM_0_JTAG_CHAIN (2)
#define CONFIG_XILINX_MDM_0_INTERCONNECT (1)
#define CONFIG_XILINX_MDM_0_BASEADDR (0x84400000)
#define CONFIG_XILINX_MDM_0_HIGHADDR (0x8440FFFF)
#define CONFIG_XILINX_MDM_0_SPLB_AWIDTH (32)
#define CONFIG_XILINX_MDM_0_SPLB_DWIDTH (32)
#define CONFIG_XILINX_MDM_0_SPLB_P2P (0)
#define CONFIG_XILINX_MDM_0_SPLB_MID_WIDTH (1)
#define CONFIG_XILINX_MDM_0_SPLB_NUM_MASTERS (2)
#define CONFIG_XILINX_MDM_0_SPLB_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MDM_0_SPLB_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MDM_0_OPB_DWIDTH (32)
#define CONFIG_XILINX_MDM_0_OPB_AWIDTH (32)
#define CONFIG_XILINX_MDM_0_MB_DBG_PORTS (1)
#define CONFIG_XILINX_MDM_0_USE_UART (1)
#define CONFIG_XILINX_MDM_0_UART_WIDTH (8)
#define CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS (0)
#define CONFIG_XILINX_MDM_0_INSTANCE "debug_module"
#define CONFIG_XILINX_MDM_0_HW_VER "1.00.d"

/* Definitions for GPIO_0 */
#define CONFIG_XILINX_GPIO_0_INSTANCE "LEDs_8Bit"
#define CONFIG_XILINX_GPIO_0_BASEADDR (0x81400000)
#define CONFIG_XILINX_GPIO_0_HIGHADDR (0x8140FFFF)
#define CONFIG_XILINX_GPIO_0_SPLB_AWIDTH (32)
#define CONFIG_XILINX_GPIO_0_SPLB_DWIDTH (32)
#define CONFIG_XILINX_GPIO_0_SPLB_P2P (0)
#define CONFIG_XILINX_GPIO_0_SPLB_MID_WIDTH (1)
#define CONFIG_XILINX_GPIO_0_SPLB_NUM_MASTERS (2)
#define CONFIG_XILINX_GPIO_0_SPLB_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_GPIO_0_SPLB_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_GPIO_0_FAMILY "spartan3a"
#define CONFIG_XILINX_GPIO_0_GPIO_WIDTH (8)
#define CONFIG_XILINX_GPIO_0_ALL_INPUTS (0)
#define CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT (0)
#define CONFIG_XILINX_GPIO_0_IS_BIDIR (0)
#define CONFIG_XILINX_GPIO_0_DOUT_DEFAULT (0x00000000)
#define CONFIG_XILINX_GPIO_0_TRI_DEFAULT (0xFFFFFFFF)
#define CONFIG_XILINX_GPIO_0_IS_DUAL (0)
#define CONFIG_XILINX_GPIO_0_ALL_INPUTS_2 (0)
#define CONFIG_XILINX_GPIO_0_IS_BIDIR_2 (1)
#define CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2 (0x00000000)
#define CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2 (0xFFFFFFFF)
#define CONFIG_XILINX_GPIO_0_INSTANCE "LEDs_8Bit"
#define CONFIG_XILINX_GPIO_0_HW_VER "1.00.a"

/* Definitions for ETHERNETLITE_0 */
#define CONFIG_XILINX_ETHERNETLITE_0_INSTANCE "Ethernet_MAC"
#define CONFIG_XILINX_ETHERNETLITE_0_FAMILY "spartan3a"
#define CONFIG_XILINX_ETHERNETLITE_0_BASEADDR (0x81000000)
#define CONFIG_XILINX_ETHERNETLITE_0_HIGHADDR (0x8100FFFF)
#define CONFIG_XILINX_ETHERNETLITE_0_SPLB_CLK_PERIOD_PS (16000)
#define CONFIG_XILINX_ETHERNETLITE_0_SPLB_AWIDTH (32)
#define CONFIG_XILINX_ETHERNETLITE_0_SPLB_DWIDTH (32)
#define CONFIG_XILINX_ETHERNETLITE_0_SPLB_P2P (0)
#define CONFIG_XILINX_ETHERNETLITE_0_SPLB_MID_WIDTH (1)
#define CONFIG_XILINX_ETHERNETLITE_0_SPLB_NUM_MASTERS (2)
#define CONFIG_XILINX_ETHERNETLITE_0_SPLB_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_ETHERNETLITE_0_SPLB_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_ETHERNETLITE_0_DUPLEX (1)
#define CONFIG_XILINX_ETHERNETLITE_0_TX_PING_PONG (0)
#define CONFIG_XILINX_ETHERNETLITE_0_RX_PING_PONG (0)
#define CONFIG_XILINX_ETHERNETLITE_0_INSTANCE "Ethernet_MAC"
#define CONFIG_XILINX_ETHERNETLITE_0_HW_VER "2.00.b"
#define CONFIG_XILINX_ETHERNETLITE_0_IRQ (1)

/* Definitions for MPMC_0 */
#define CONFIG_XILINX_MPMC_0_INSTANCE "DDR2_SDRAM"
#define CONFIG_XILINX_MPMC_0_FAMILY "spartan3a"
#define CONFIG_XILINX_MPMC_0_NUM_PORTS (3)
#define CONFIG_XILINX_MPMC_0_ALL_PIMS_SHARE_ADDRESSES (1)
#define CONFIG_XILINX_MPMC_0_MPMC_BASEADDR (0x8C000000)
#define CONFIG_XILINX_MPMC_0_MPMC_HIGHADDR (0x8FFFFFFF)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_MPMC_CTRL_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_MPMC_CTRL_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_MPMC_CTRL_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_MPMC_CTRL_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_MPMC_CTRL_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MPMC_0_MPMC_CTRL_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_MPMC_CTRL_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_MPMC_CTRL_P2P (1)
#define CONFIG_XILINX_MPMC_0_MPMC_CTRL_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_MPMC_CTRL_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_NUM_IDELAYCTRL (1)
#define CONFIG_XILINX_MPMC_0_IDELAYCTRL_LOC "NOT_SET"
#define CONFIG_XILINX_MPMC_0_MAX_REQ_ALLOWED (1)
#define CONFIG_XILINX_MPMC_0_ARB_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_WR_DATAPATH_TML_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_RD_DATAPATH_TML_MAX_FANOUT (0)
#define CONFIG_XILINX_MPMC_0_ARB_USE_DEFAULT (0)
#define CONFIG_XILINX_MPMC_0_ARB0_ALGO "ROUND_ROBIN"
#define CONFIG_XILINX_MPMC_0_ARB0_NUM_SLOTS (8)
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT0 "01234567"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT1 "12345670"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT2 "23456701"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT3 "34567012"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT4 "45670123"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT5 "56701234"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT6 "67012345"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT7 "70123456"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT8 "01234567"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT9 "12345670"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT10 "23456701"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT11 "34567012"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT12 "45670123"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT13 "56701234"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT14 "67012345"
#define CONFIG_XILINX_MPMC_0_ARB0_SLOT15 "70123456"
#define CONFIG_XILINX_MPMC_0_PM_ENABLE (0)
#define CONFIG_XILINX_MPMC_0_PM_DC_WIDTH (48)
#define CONFIG_XILINX_MPMC_0_PM_GC_CNTR (1)
#define CONFIG_XILINX_MPMC_0_PM_GC_WIDTH (48)
#define CONFIG_XILINX_MPMC_0_PM_SHIFT_CNT_BY (1)
#define CONFIG_XILINX_MPMC_0_SKIP_SIM_INIT_DELAY (0)
#define CONFIG_XILINX_MPMC_0_USE_STATIC_PHY (0)
#define CONFIG_XILINX_MPMC_0_STATIC_PHY_RDDATA_CLK_SEL (0)
#define CONFIG_XILINX_MPMC_0_STATIC_PHY_RDDATA_SWAP_RISE (0)
#define CONFIG_XILINX_MPMC_0_STATIC_PHY_RDEN_DELAY (5)
#define CONFIG_XILINX_MPMC_0_DEBUG_REG_ENABLE (0)
#define CONFIG_XILINX_MPMC_0_SPECIAL_BOARD "S3A_STKIT"
#define CONFIG_XILINX_MPMC_0_MEM_TYPE "DDR2"
#define CONFIG_XILINX_MPMC_0_MEM_PARTNO "MT47H32M16-3"
#define CONFIG_XILINX_MPMC_0_MEM_PART_DATA_DEPTH (32)
#define CONFIG_XILINX_MPMC_0_MEM_PART_DATA_WIDTH (16)
#define CONFIG_XILINX_MPMC_0_MEM_PART_NUM_BANK_BITS (2)
#define CONFIG_XILINX_MPMC_0_MEM_PART_NUM_ROW_BITS (13)
#define CONFIG_XILINX_MPMC_0_MEM_PART_NUM_COL_BITS (10)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TRAS (40000)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TRASMAX (70000000)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TRC (55000)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TRCD (15000)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TDQSS (1)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TWR (15000)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TRP (15000)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TMRD (2)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TRRD (10000)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TRFC (105000)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TREFI (7800000)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TAL (0)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TCCD (2)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TWTR (7500)
#define CONFIG_XILINX_MPMC_0_MEM_PART_TRTP (7500)
#define CONFIG_XILINX_MPMC_0_MEM_PART_CAS_A_FMAX (200)
#define CONFIG_XILINX_MPMC_0_MEM_PART_CAS_A (3)
#define CONFIG_XILINX_MPMC_0_MEM_PART_CAS_B_FMAX (266)
#define CONFIG_XILINX_MPMC_0_MEM_PART_CAS_B (4)
#define CONFIG_XILINX_MPMC_0_MEM_PART_CAS_C_FMAX (333)
#define CONFIG_XILINX_MPMC_0_MEM_PART_CAS_C (5)
#define CONFIG_XILINX_MPMC_0_MEM_PART_CAS_D_FMAX (0)
#define CONFIG_XILINX_MPMC_0_MEM_PART_CAS_D (0)
#define CONFIG_XILINX_MPMC_0_MEM_CAS_LATENCY0 (3)
#define CONFIG_XILINX_MPMC_0_MEM_ODT_TYPE (0)
#define CONFIG_XILINX_MPMC_0_MEM_REDUCED_DRV (0)
#define CONFIG_XILINX_MPMC_0_MEM_REG_DIMM (0)
#define CONFIG_XILINX_MPMC_0_MPMC_CLK0_PERIOD_PS (8000)
#define CONFIG_XILINX_MPMC_0_MEM_CLK_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_MEM_ODT_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_MEM_CE_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_MEM_CS_N_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_MEM_ADDR_WIDTH (13)
#define CONFIG_XILINX_MPMC_0_MEM_BANKADDR_WIDTH (2)
#define CONFIG_XILINX_MPMC_0_MEM_DATA_WIDTH (16)
#define CONFIG_XILINX_MPMC_0_MEM_BITS_DATA_PER_DQS (8)
#define CONFIG_XILINX_MPMC_0_MEM_DM_WIDTH (2)
#define CONFIG_XILINX_MPMC_0_MEM_DQS_WIDTH (2)
#define CONFIG_XILINX_MPMC_0_MEM_NUM_DIMMS (1)
#define CONFIG_XILINX_MPMC_0_MEM_NUM_RANKS (1)
#define CONFIG_XILINX_MPMC_0_MEM_DQS_IO_COL (0x0)
#define CONFIG_XILINX_MPMC_0_MEM_DQ_IO_MS (0x0)
#define CONFIG_XILINX_MPMC_0_DDR2_DQSN_ENABLE (1)
#define CONFIG_XILINX_MPMC_0_INCLUDE_ECC_SUPPORT (0)
#define CONFIG_XILINX_MPMC_0_ECC_DEFAULT_ON (1)
#define CONFIG_XILINX_MPMC_0_INCLUDE_ECC_TEST (0)
#define CONFIG_XILINX_MPMC_0_ECC_SEC_THRESHOLD (1)
#define CONFIG_XILINX_MPMC_0_ECC_DEC_THRESHOLD (1)
#define CONFIG_XILINX_MPMC_0_ECC_PEC_THRESHOLD (1)
#define CONFIG_XILINX_MPMC_0_ECC_DATA_WIDTH (0)
#define CONFIG_XILINX_MPMC_0_ECC_DM_WIDTH (0)
#define CONFIG_XILINX_MPMC_0_ECC_DQS_WIDTH (0)
#define CONFIG_XILINX_MPMC_0_TBY4TAPVALUE (9999)
#define CONFIG_XILINX_MPMC_0_PIM0_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_PIM0_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM0_OFFSET (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM0_DATA_WIDTH (64)
#define CONFIG_XILINX_MPMC_0_PIM0_BASETYPE (1)
#define CONFIG_XILINX_MPMC_0_PIM0_SUBTYPE "IXCL"
#define CONFIG_XILINX_MPMC_0_XCL0_LINESIZE (4)
#define CONFIG_XILINX_MPMC_0_XCL0_WRITEXFER (0)
#define CONFIG_XILINX_MPMC_0_XCL0_PIPE_STAGES (3)
#define CONFIG_XILINX_MPMC_0_SPLB0_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SPLB0_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB0_NATIVE_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB0_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SPLB0_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SPLB0_P2P (1)
#define CONFIG_XILINX_MPMC_0_SPLB0_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SPLB0_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL0_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL0_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL0_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL0_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL0_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL0_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL0_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL0_P2P (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL0_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL0_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA0_COMPLETED_ERR_TX (1)
#define CONFIG_XILINX_MPMC_0_SDMA0_COMPLETED_ERR_RX (1)
#define CONFIG_XILINX_MPMC_0_SDMA0_PRESCALAR (1023)
#define CONFIG_XILINX_MPMC_0_SDMA0_PI2LL_CLK_RATIO (1)
#define CONFIG_XILINX_MPMC_0_PPC440MC0_BURST_LENGTH (4)
#define CONFIG_XILINX_MPMC_0_PPC440MC0_PIPE_STAGES (1)
#define CONFIG_XILINX_MPMC_0_VFBC0_CMD_FIFO_DEPTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC0_CMD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_VFBC0_RDWD_DATA_WIDTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC0_RDWD_FIFO_DEPTH (1024)
#define CONFIG_XILINX_MPMC_0_VFBC0_RD_AEMPTY_WD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_PI0_RD_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI0_WR_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI0_ADDRACK_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI0_RD_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI0_RD_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI0_WR_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI0_WR_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI0_PM_USED (1)
#define CONFIG_XILINX_MPMC_0_PI0_PM_DC_CNTR (1)
#define CONFIG_XILINX_MPMC_0_PIM1_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_PIM1_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM1_OFFSET (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM1_DATA_WIDTH (64)
#define CONFIG_XILINX_MPMC_0_PIM1_BASETYPE (1)
#define CONFIG_XILINX_MPMC_0_PIM1_SUBTYPE "DXCL"
#define CONFIG_XILINX_MPMC_0_XCL1_LINESIZE (4)
#define CONFIG_XILINX_MPMC_0_XCL1_WRITEXFER (1)
#define CONFIG_XILINX_MPMC_0_XCL1_PIPE_STAGES (3)
#define CONFIG_XILINX_MPMC_0_SPLB1_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SPLB1_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB1_NATIVE_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB1_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SPLB1_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SPLB1_P2P (1)
#define CONFIG_XILINX_MPMC_0_SPLB1_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SPLB1_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL1_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL1_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL1_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL1_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL1_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL1_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL1_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL1_P2P (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL1_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL1_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA1_COMPLETED_ERR_TX (1)
#define CONFIG_XILINX_MPMC_0_SDMA1_COMPLETED_ERR_RX (1)
#define CONFIG_XILINX_MPMC_0_SDMA1_PRESCALAR (1023)
#define CONFIG_XILINX_MPMC_0_SDMA1_PI2LL_CLK_RATIO (1)
#define CONFIG_XILINX_MPMC_0_PPC440MC1_BURST_LENGTH (4)
#define CONFIG_XILINX_MPMC_0_PPC440MC1_PIPE_STAGES (1)
#define CONFIG_XILINX_MPMC_0_VFBC1_CMD_FIFO_DEPTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC1_CMD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_VFBC1_RDWD_DATA_WIDTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC1_RDWD_FIFO_DEPTH (1024)
#define CONFIG_XILINX_MPMC_0_VFBC1_RD_AEMPTY_WD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_PI1_RD_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI1_WR_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI1_ADDRACK_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI1_RD_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI1_RD_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI1_WR_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI1_WR_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI1_PM_USED (1)
#define CONFIG_XILINX_MPMC_0_PI1_PM_DC_CNTR (1)
#define CONFIG_XILINX_MPMC_0_PIM2_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_PIM2_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM2_OFFSET (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM2_DATA_WIDTH (64)
#define CONFIG_XILINX_MPMC_0_PIM2_BASETYPE (2)
#define CONFIG_XILINX_MPMC_0_PIM2_SUBTYPE "PLB"
#define CONFIG_XILINX_MPMC_0_XCL2_LINESIZE (4)
#define CONFIG_XILINX_MPMC_0_XCL2_WRITEXFER (1)
#define CONFIG_XILINX_MPMC_0_XCL2_PIPE_STAGES (3)
#define CONFIG_XILINX_MPMC_0_SPLB2_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SPLB2_DWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SPLB2_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SPLB2_NUM_MASTERS (2)
#define CONFIG_XILINX_MPMC_0_SPLB2_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SPLB2_P2P (0)
#define CONFIG_XILINX_MPMC_0_SPLB2_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SPLB2_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL2_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL2_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL2_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL2_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL2_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL2_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL2_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL2_P2P (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL2_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL2_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA2_COMPLETED_ERR_TX (1)
#define CONFIG_XILINX_MPMC_0_SDMA2_COMPLETED_ERR_RX (1)
#define CONFIG_XILINX_MPMC_0_SDMA2_PRESCALAR (1023)
#define CONFIG_XILINX_MPMC_0_SDMA2_PI2LL_CLK_RATIO (1)
#define CONFIG_XILINX_MPMC_0_PPC440MC2_BURST_LENGTH (4)
#define CONFIG_XILINX_MPMC_0_PPC440MC2_PIPE_STAGES (1)
#define CONFIG_XILINX_MPMC_0_VFBC2_CMD_FIFO_DEPTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC2_CMD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_VFBC2_RDWD_DATA_WIDTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC2_RDWD_FIFO_DEPTH (1024)
#define CONFIG_XILINX_MPMC_0_VFBC2_RD_AEMPTY_WD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_PI2_RD_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI2_WR_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI2_ADDRACK_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI2_RD_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI2_RD_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI2_WR_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI2_WR_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI2_PM_USED (1)
#define CONFIG_XILINX_MPMC_0_PI2_PM_DC_CNTR (1)
#define CONFIG_XILINX_MPMC_0_PIM3_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_PIM3_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM3_OFFSET (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM3_DATA_WIDTH (64)
#define CONFIG_XILINX_MPMC_0_PIM3_BASETYPE (0)
#define CONFIG_XILINX_MPMC_0_PIM3_SUBTYPE "INACTIVE"
#define CONFIG_XILINX_MPMC_0_XCL3_LINESIZE (4)
#define CONFIG_XILINX_MPMC_0_XCL3_WRITEXFER (1)
#define CONFIG_XILINX_MPMC_0_XCL3_PIPE_STAGES (3)
#define CONFIG_XILINX_MPMC_0_SPLB3_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SPLB3_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB3_NATIVE_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB3_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SPLB3_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SPLB3_P2P (1)
#define CONFIG_XILINX_MPMC_0_SPLB3_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SPLB3_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL3_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL3_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL3_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL3_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL3_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL3_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL3_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL3_P2P (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL3_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL3_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA3_COMPLETED_ERR_TX (1)
#define CONFIG_XILINX_MPMC_0_SDMA3_COMPLETED_ERR_RX (1)
#define CONFIG_XILINX_MPMC_0_SDMA3_PRESCALAR (1023)
#define CONFIG_XILINX_MPMC_0_SDMA3_PI2LL_CLK_RATIO (1)
#define CONFIG_XILINX_MPMC_0_PPC440MC3_BURST_LENGTH (4)
#define CONFIG_XILINX_MPMC_0_PPC440MC3_PIPE_STAGES (1)
#define CONFIG_XILINX_MPMC_0_VFBC3_CMD_FIFO_DEPTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC3_CMD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_VFBC3_RDWD_DATA_WIDTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC3_RDWD_FIFO_DEPTH (1024)
#define CONFIG_XILINX_MPMC_0_VFBC3_RD_AEMPTY_WD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_PI3_RD_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI3_WR_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI3_ADDRACK_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI3_RD_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI3_RD_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI3_WR_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI3_WR_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI3_PM_USED (1)
#define CONFIG_XILINX_MPMC_0_PI3_PM_DC_CNTR (1)
#define CONFIG_XILINX_MPMC_0_PIM4_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_PIM4_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM4_OFFSET (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM4_DATA_WIDTH (64)
#define CONFIG_XILINX_MPMC_0_PIM4_BASETYPE (0)
#define CONFIG_XILINX_MPMC_0_PIM4_SUBTYPE "INACTIVE"
#define CONFIG_XILINX_MPMC_0_XCL4_LINESIZE (4)
#define CONFIG_XILINX_MPMC_0_XCL4_WRITEXFER (1)
#define CONFIG_XILINX_MPMC_0_XCL4_PIPE_STAGES (3)
#define CONFIG_XILINX_MPMC_0_SPLB4_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SPLB4_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB4_NATIVE_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB4_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SPLB4_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SPLB4_P2P (1)
#define CONFIG_XILINX_MPMC_0_SPLB4_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SPLB4_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL4_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL4_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL4_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL4_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL4_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL4_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL4_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL4_P2P (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL4_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL4_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA4_COMPLETED_ERR_TX (1)
#define CONFIG_XILINX_MPMC_0_SDMA4_COMPLETED_ERR_RX (1)
#define CONFIG_XILINX_MPMC_0_SDMA4_PRESCALAR (1023)
#define CONFIG_XILINX_MPMC_0_SDMA4_PI2LL_CLK_RATIO (1)
#define CONFIG_XILINX_MPMC_0_PPC440MC4_BURST_LENGTH (4)
#define CONFIG_XILINX_MPMC_0_PPC440MC4_PIPE_STAGES (1)
#define CONFIG_XILINX_MPMC_0_VFBC4_CMD_FIFO_DEPTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC4_CMD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_VFBC4_RDWD_DATA_WIDTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC4_RDWD_FIFO_DEPTH (1024)
#define CONFIG_XILINX_MPMC_0_VFBC4_RD_AEMPTY_WD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_PI4_RD_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI4_WR_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI4_ADDRACK_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI4_RD_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI4_RD_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI4_WR_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI4_WR_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI4_PM_USED (1)
#define CONFIG_XILINX_MPMC_0_PI4_PM_DC_CNTR (1)
#define CONFIG_XILINX_MPMC_0_PIM5_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_PIM5_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM5_OFFSET (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM5_DATA_WIDTH (64)
#define CONFIG_XILINX_MPMC_0_PIM5_BASETYPE (0)
#define CONFIG_XILINX_MPMC_0_PIM5_SUBTYPE "INACTIVE"
#define CONFIG_XILINX_MPMC_0_XCL5_LINESIZE (4)
#define CONFIG_XILINX_MPMC_0_XCL5_WRITEXFER (1)
#define CONFIG_XILINX_MPMC_0_XCL5_PIPE_STAGES (3)
#define CONFIG_XILINX_MPMC_0_SPLB5_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SPLB5_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB5_NATIVE_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB5_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SPLB5_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SPLB5_P2P (1)
#define CONFIG_XILINX_MPMC_0_SPLB5_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SPLB5_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL5_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL5_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL5_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL5_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL5_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL5_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL5_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL5_P2P (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL5_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL5_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA5_COMPLETED_ERR_TX (1)
#define CONFIG_XILINX_MPMC_0_SDMA5_COMPLETED_ERR_RX (1)
#define CONFIG_XILINX_MPMC_0_SDMA5_PRESCALAR (1023)
#define CONFIG_XILINX_MPMC_0_SDMA5_PI2LL_CLK_RATIO (1)
#define CONFIG_XILINX_MPMC_0_PPC440MC5_BURST_LENGTH (4)
#define CONFIG_XILINX_MPMC_0_PPC440MC5_PIPE_STAGES (1)
#define CONFIG_XILINX_MPMC_0_VFBC5_CMD_FIFO_DEPTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC5_CMD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_VFBC5_RDWD_DATA_WIDTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC5_RDWD_FIFO_DEPTH (1024)
#define CONFIG_XILINX_MPMC_0_VFBC5_RD_AEMPTY_WD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_PI5_RD_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI5_WR_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI5_ADDRACK_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI5_RD_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI5_RD_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI5_WR_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI5_WR_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI5_PM_USED (1)
#define CONFIG_XILINX_MPMC_0_PI5_PM_DC_CNTR (1)
#define CONFIG_XILINX_MPMC_0_PIM6_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_PIM6_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM6_OFFSET (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM6_DATA_WIDTH (64)
#define CONFIG_XILINX_MPMC_0_PIM6_BASETYPE (0)
#define CONFIG_XILINX_MPMC_0_PIM6_SUBTYPE "INACTIVE"
#define CONFIG_XILINX_MPMC_0_XCL6_LINESIZE (4)
#define CONFIG_XILINX_MPMC_0_XCL6_WRITEXFER (1)
#define CONFIG_XILINX_MPMC_0_XCL6_PIPE_STAGES (3)
#define CONFIG_XILINX_MPMC_0_SPLB6_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SPLB6_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB6_NATIVE_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB6_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SPLB6_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SPLB6_P2P (1)
#define CONFIG_XILINX_MPMC_0_SPLB6_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SPLB6_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL6_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL6_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL6_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL6_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL6_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL6_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL6_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL6_P2P (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL6_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL6_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA6_COMPLETED_ERR_TX (1)
#define CONFIG_XILINX_MPMC_0_SDMA6_COMPLETED_ERR_RX (1)
#define CONFIG_XILINX_MPMC_0_SDMA6_PRESCALAR (1023)
#define CONFIG_XILINX_MPMC_0_SDMA6_PI2LL_CLK_RATIO (1)
#define CONFIG_XILINX_MPMC_0_PPC440MC6_BURST_LENGTH (4)
#define CONFIG_XILINX_MPMC_0_PPC440MC6_PIPE_STAGES (1)
#define CONFIG_XILINX_MPMC_0_VFBC6_CMD_FIFO_DEPTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC6_CMD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_VFBC6_RDWD_DATA_WIDTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC6_RDWD_FIFO_DEPTH (1024)
#define CONFIG_XILINX_MPMC_0_VFBC6_RD_AEMPTY_WD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_PI6_RD_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI6_WR_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI6_ADDRACK_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI6_RD_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI6_RD_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI6_WR_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI6_WR_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI6_PM_USED (1)
#define CONFIG_XILINX_MPMC_0_PI6_PM_DC_CNTR (1)
#define CONFIG_XILINX_MPMC_0_PIM7_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_PIM7_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM7_OFFSET (0x00000000)
#define CONFIG_XILINX_MPMC_0_PIM7_DATA_WIDTH (64)
#define CONFIG_XILINX_MPMC_0_PIM7_BASETYPE (0)
#define CONFIG_XILINX_MPMC_0_PIM7_SUBTYPE "INACTIVE"
#define CONFIG_XILINX_MPMC_0_XCL7_LINESIZE (4)
#define CONFIG_XILINX_MPMC_0_XCL7_WRITEXFER (1)
#define CONFIG_XILINX_MPMC_0_XCL7_PIPE_STAGES (3)
#define CONFIG_XILINX_MPMC_0_SPLB7_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SPLB7_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB7_NATIVE_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SPLB7_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SPLB7_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SPLB7_P2P (1)
#define CONFIG_XILINX_MPMC_0_SPLB7_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SPLB7_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL7_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL7_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL7_AWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL7_DWIDTH (64)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL7_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL7_NUM_MASTERS (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL7_MID_WIDTH (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL7_P2P (1)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL7_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_MPMC_0_SDMA_CTRL7_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MPMC_0_SDMA7_COMPLETED_ERR_TX (1)
#define CONFIG_XILINX_MPMC_0_SDMA7_COMPLETED_ERR_RX (1)
#define CONFIG_XILINX_MPMC_0_SDMA7_PRESCALAR (1023)
#define CONFIG_XILINX_MPMC_0_SDMA7_PI2LL_CLK_RATIO (1)
#define CONFIG_XILINX_MPMC_0_PPC440MC7_BURST_LENGTH (4)
#define CONFIG_XILINX_MPMC_0_PPC440MC7_PIPE_STAGES (1)
#define CONFIG_XILINX_MPMC_0_VFBC7_CMD_FIFO_DEPTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC7_CMD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_VFBC7_RDWD_DATA_WIDTH (32)
#define CONFIG_XILINX_MPMC_0_VFBC7_RDWD_FIFO_DEPTH (1024)
#define CONFIG_XILINX_MPMC_0_VFBC7_RD_AEMPTY_WD_AFULL_COUNT (3)
#define CONFIG_XILINX_MPMC_0_PI7_RD_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI7_WR_FIFO_TYPE "BRAM"
#define CONFIG_XILINX_MPMC_0_PI7_ADDRACK_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI7_RD_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI7_RD_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI7_WR_FIFO_APP_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI7_WR_FIFO_MEM_PIPELINE (1)
#define CONFIG_XILINX_MPMC_0_PI7_PM_USED (1)
#define CONFIG_XILINX_MPMC_0_PI7_PM_DC_CNTR (1)
#define CONFIG_XILINX_MPMC_0_WR_TRAINING_PORT (1)
#define CONFIG_XILINX_MPMC_0_ARB_BRAM_INIT_00 (0x00FFFFFF)
#define CONFIG_XILINX_MPMC_0_ARB_BRAM_INIT_01 (0x00FFFFFF)
#define CONFIG_XILINX_MPMC_0_ARB_BRAM_INIT_02 (0x00FFFFFF)
#define CONFIG_XILINX_MPMC_0_ARB_BRAM_INIT_03 (0x00FFFFFF)
#define CONFIG_XILINX_MPMC_0_ARB_BRAM_INIT_04 (0x00FFFFFF)
#define CONFIG_XILINX_MPMC_0_ARB_BRAM_INIT_05 (0x00FFFFFF)
#define CONFIG_XILINX_MPMC_0_ARB_BRAM_INIT_06 (0x00FFFFFF)
#define CONFIG_XILINX_MPMC_0_ARB_BRAM_INIT_07 (0x00FFFFFF)
#define CONFIG_XILINX_MPMC_0_TWR (15000)
#define CONFIG_XILINX_MPMC_0_CTRL_AP_COL_DELAY (0x00000001)
#define CONFIG_XILINX_MPMC_0_CTRL_AP_PI_ADDR_CE_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_AP_PORT_SELECT_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_AP_PIPELINE1_CE_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_DP_LOAD_RDWDADDR_DELAY (0x00000002)
#define CONFIG_XILINX_MPMC_0_CTRL_DP_RDFIFO_WHICHPORT_DELAY (0x0000000C)
#define CONFIG_XILINX_MPMC_0_CTRL_DP_SIZE_DELAY (0x00000002)
#define CONFIG_XILINX_MPMC_0_CTRL_DP_WRFIFO_WHICHPORT_DELAY (0x00000004)
#define CONFIG_XILINX_MPMC_0_CTRL_PHYIF_DUMMYREADSTART_DELAY (0x00000005)
#define CONFIG_XILINX_MPMC_0_CTRL_Q0_DELAY (0x00000001)
#define CONFIG_XILINX_MPMC_0_CTRL_Q1_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q2_DELAY (0x00000002)
#define CONFIG_XILINX_MPMC_0_CTRL_Q3_DELAY (0x00000002)
#define CONFIG_XILINX_MPMC_0_CTRL_Q4_DELAY (0x00000002)
#define CONFIG_XILINX_MPMC_0_CTRL_Q5_DELAY (0x00000002)
#define CONFIG_XILINX_MPMC_0_CTRL_Q6_DELAY (0x00000005)
#define CONFIG_XILINX_MPMC_0_CTRL_Q7_DELAY (0x00000001)
#define CONFIG_XILINX_MPMC_0_CTRL_Q8_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q9_DELAY (0x00000001)
#define CONFIG_XILINX_MPMC_0_CTRL_Q10_DELAY (0x00000001)
#define CONFIG_XILINX_MPMC_0_CTRL_Q11_DELAY (0x00000001)
#define CONFIG_XILINX_MPMC_0_CTRL_Q12_DELAY (0x00000001)
#define CONFIG_XILINX_MPMC_0_CTRL_Q13_DELAY (0x00000001)
#define CONFIG_XILINX_MPMC_0_CTRL_Q14_DELAY (0x00000001)
#define CONFIG_XILINX_MPMC_0_CTRL_Q15_DELAY (0x00000001)
#define CONFIG_XILINX_MPMC_0_CTRL_Q16_DELAY (0x00000001)
#define CONFIG_XILINX_MPMC_0_CTRL_Q17_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q18_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q19_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q20_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q21_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q22_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q23_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q24_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q25_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q26_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q27_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q28_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q29_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q30_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q31_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q32_DELAY (0x00000002)
#define CONFIG_XILINX_MPMC_0_CTRL_Q33_DELAY (0x00000001)
#define CONFIG_XILINX_MPMC_0_CTRL_Q34_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_CTRL_Q35_DELAY (0x00000000)
#define CONFIG_XILINX_MPMC_0_SKIP_1_VALUE (0x001)
#define CONFIG_XILINX_MPMC_0_SKIP_2_VALUE (0x001)
#define CONFIG_XILINX_MPMC_0_SKIP_3_VALUE (0x001)
#define CONFIG_XILINX_MPMC_0_SKIP_4_VALUE (0x001)
#define CONFIG_XILINX_MPMC_0_SKIP_5_VALUE (0x001)
#define CONFIG_XILINX_MPMC_0_SKIP_6_VALUE (0x001)
#define CONFIG_XILINX_MPMC_0_SKIP_7_VALUE (0x001)
#define CONFIG_XILINX_MPMC_0_B16_REPEAT_CNT (0)
#define CONFIG_XILINX_MPMC_0_B32_REPEAT_CNT (6)
#define CONFIG_XILINX_MPMC_0_B64_REPEAT_CNT (14)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL0 (0x00000000)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL0 (0x0000000B)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL1 (0x0000000C)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL1 (0x00000013)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL2 (0x00000014)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL2 (0x0000001F)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL3 (0x00000020)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL3 (0x00000027)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL4 (0x00000028)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL4 (0x00000035)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL5 (0x00000036)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL5 (0x0000003E)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL6 (0x0000003F)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL6 (0x00000050)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL7 (0x00000051)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL7 (0x0000005D)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL8 (0x0000005E)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL8 (0x00000077)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL9 (0x00000078)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL9 (0x0000008C)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL10 (0x0000008D)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL10 (0x0000009E)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL11 (0x0000009F)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL11 (0x000000AB)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL12 (0x000000AC)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL12 (0x000000BD)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL13 (0x000000BE)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL13 (0x000000CA)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL14 (0x000000CB)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL14 (0x000000DB)
#define CONFIG_XILINX_MPMC_0_BASEADDR_CTRL15 (0x000000DC)
#define CONFIG_XILINX_MPMC_0_HIGHADDR_CTRL15 (0x000000DD)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_3F (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_3E (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_3D (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_3C (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_3B (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_3A (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_39 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_38 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_37 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_36 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_35 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_34 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_33 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_32 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_31 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_30 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_2F (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_2E (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_2D (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_2C (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_2B (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_2A (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_29 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_28 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_27 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_26 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_25 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_24 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_23 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_22 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_21 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_20 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_1F (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_1E (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_1D (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_1C (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_1B (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_1A (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_19 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_18 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_17 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_16 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_15 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_14 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_13 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_12 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_11 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_10 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_0F (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_0E (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_0D (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_0C (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_0B (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_0A (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_09 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_08 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_07 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_06 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_05 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_04 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_03 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_02 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_01 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INIT_00 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_SRVAL (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INITP_07 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INITP_06 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INITP_05 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INITP_04 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INITP_03 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INITP_02 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INITP_01 (0x0)
#define CONFIG_XILINX_MPMC_0_CTRL_BRAM_INITP_00 (0x0)
#define CONFIG_XILINX_MPMC_0_INSTANCE "DDR2_SDRAM"
#define CONFIG_XILINX_MPMC_0_HW_VER "4.03.a"

/* Definitions for MCH_EMC_0 */
#define CONFIG_XILINX_MCH_EMC_0_INSTANCE "FLASH"
#define CONFIG_XILINX_MCH_EMC_0_FAMILY "spartan3a"
#define CONFIG_XILINX_MCH_EMC_0_NUM_BANKS_MEM (1)
#define CONFIG_XILINX_MCH_EMC_0_NUM_CHANNELS (0)
#define CONFIG_XILINX_MCH_EMC_0_PRIORITY_MODE (0)
#define CONFIG_XILINX_MCH_EMC_0_INCLUDE_PLB_IPIF (1)
#define CONFIG_XILINX_MCH_EMC_0_INCLUDE_WRBUF (1)
#define CONFIG_XILINX_MCH_EMC_0_SPLB_MID_WIDTH (1)
#define CONFIG_XILINX_MCH_EMC_0_SPLB_NUM_MASTERS (2)
#define CONFIG_XILINX_MCH_EMC_0_SPLB_P2P (0)
#define CONFIG_XILINX_MCH_EMC_0_SPLB_DWIDTH (32)
#define CONFIG_XILINX_MCH_EMC_0_MCH_SPLB_AWIDTH (32)
#define CONFIG_XILINX_MCH_EMC_0_SPLB_SMALLEST_MASTER (32)
#define CONFIG_XILINX_MCH_EMC_0_MCH_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_MCH_EMC_0_MCH_PLB_CLK_PERIOD_PS (16000)
#define CONFIG_XILINX_MCH_EMC_0_MEM0_BASEADDR (0x88400000)
#define CONFIG_XILINX_MCH_EMC_0_MEM0_HIGHADDR (0x887FFFFF)
#define CONFIG_XILINX_MCH_EMC_0_MEM1_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MCH_EMC_0_MEM1_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MCH_EMC_0_MEM2_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MCH_EMC_0_MEM2_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MCH_EMC_0_MEM3_BASEADDR (0xFFFFFFFF)
#define CONFIG_XILINX_MCH_EMC_0_MEM3_HIGHADDR (0x00000000)
#define CONFIG_XILINX_MCH_EMC_0_INCLUDE_NEGEDGE_IOREGS (0)
#define CONFIG_XILINX_MCH_EMC_0_MEM0_WIDTH (16)
#define CONFIG_XILINX_MCH_EMC_0_MEM1_WIDTH (32)
#define CONFIG_XILINX_MCH_EMC_0_MEM2_WIDTH (32)
#define CONFIG_XILINX_MCH_EMC_0_MEM3_WIDTH (32)
#define CONFIG_XILINX_MCH_EMC_0_MAX_MEM_WIDTH (16)
#define CONFIG_XILINX_MCH_EMC_0_INCLUDE_DATAWIDTH_MATCHING_0 (1)
#define CONFIG_XILINX_MCH_EMC_0_INCLUDE_DATAWIDTH_MATCHING_1 (0)
#define CONFIG_XILINX_MCH_EMC_0_INCLUDE_DATAWIDTH_MATCHING_2 (0)
#define CONFIG_XILINX_MCH_EMC_0_INCLUDE_DATAWIDTH_MATCHING_3 (0)
#define CONFIG_XILINX_MCH_EMC_0_SYNCH_MEM_0 (0)
#define CONFIG_XILINX_MCH_EMC_0_SYNCH_PIPEDELAY_0 (2)
#define CONFIG_XILINX_MCH_EMC_0_TCEDV_PS_MEM_0 (70000)
#define CONFIG_XILINX_MCH_EMC_0_TAVDV_PS_MEM_0 (70000)
#define CONFIG_XILINX_MCH_EMC_0_THZCE_PS_MEM_0 (25000)
#define CONFIG_XILINX_MCH_EMC_0_THZOE_PS_MEM_0 (25000)
#define CONFIG_XILINX_MCH_EMC_0_TWC_PS_MEM_0 (70000)
#define CONFIG_XILINX_MCH_EMC_0_TWP_PS_MEM_0 (45000)
#define CONFIG_XILINX_MCH_EMC_0_TLZWE_PS_MEM_0 (5000)
#define CONFIG_XILINX_MCH_EMC_0_SYNCH_MEM_1 (0)
#define CONFIG_XILINX_MCH_EMC_0_SYNCH_PIPEDELAY_1 (2)
#define CONFIG_XILINX_MCH_EMC_0_TCEDV_PS_MEM_1 (15000)
#define CONFIG_XILINX_MCH_EMC_0_TAVDV_PS_MEM_1 (15000)
#define CONFIG_XILINX_MCH_EMC_0_THZCE_PS_MEM_1 (7000)
#define CONFIG_XILINX_MCH_EMC_0_THZOE_PS_MEM_1 (7000)
#define CONFIG_XILINX_MCH_EMC_0_TWC_PS_MEM_1 (15000)
#define CONFIG_XILINX_MCH_EMC_0_TWP_PS_MEM_1 (12000)
#define CONFIG_XILINX_MCH_EMC_0_TLZWE_PS_MEM_1 (0)
#define CONFIG_XILINX_MCH_EMC_0_SYNCH_MEM_2 (0)
#define CONFIG_XILINX_MCH_EMC_0_SYNCH_PIPEDELAY_2 (2)
#define CONFIG_XILINX_MCH_EMC_0_TCEDV_PS_MEM_2 (15000)
#define CONFIG_XILINX_MCH_EMC_0_TAVDV_PS_MEM_2 (15000)
#define CONFIG_XILINX_MCH_EMC_0_THZCE_PS_MEM_2 (7000)
#define CONFIG_XILINX_MCH_EMC_0_THZOE_PS_MEM_2 (7000)
#define CONFIG_XILINX_MCH_EMC_0_TWC_PS_MEM_2 (15000)
#define CONFIG_XILINX_MCH_EMC_0_TWP_PS_MEM_2 (12000)
#define CONFIG_XILINX_MCH_EMC_0_TLZWE_PS_MEM_2 (0)
#define CONFIG_XILINX_MCH_EMC_0_SYNCH_MEM_3 (0)
#define CONFIG_XILINX_MCH_EMC_0_SYNCH_PIPEDELAY_3 (2)
#define CONFIG_XILINX_MCH_EMC_0_TCEDV_PS_MEM_3 (15000)
#define CONFIG_XILINX_MCH_EMC_0_TAVDV_PS_MEM_3 (15000)
#define CONFIG_XILINX_MCH_EMC_0_THZCE_PS_MEM_3 (7000)
#define CONFIG_XILINX_MCH_EMC_0_THZOE_PS_MEM_3 (7000)
#define CONFIG_XILINX_MCH_EMC_0_TWC_PS_MEM_3 (15000)
#define CONFIG_XILINX_MCH_EMC_0_TWP_PS_MEM_3 (12000)
#define CONFIG_XILINX_MCH_EMC_0_TLZWE_PS_MEM_3 (0)
#define CONFIG_XILINX_MCH_EMC_0_MCH0_PROTOCOL (0)
#define CONFIG_XILINX_MCH_EMC_0_MCH0_ACCESSBUF_DEPTH (16)
#define CONFIG_XILINX_MCH_EMC_0_MCH0_RDDATABUF_DEPTH (16)
#define CONFIG_XILINX_MCH_EMC_0_MCH1_PROTOCOL (0)
#define CONFIG_XILINX_MCH_EMC_0_MCH1_ACCESSBUF_DEPTH (16)
#define CONFIG_XILINX_MCH_EMC_0_MCH1_RDDATABUF_DEPTH (16)
#define CONFIG_XILINX_MCH_EMC_0_MCH2_PROTOCOL (0)
#define CONFIG_XILINX_MCH_EMC_0_MCH2_ACCESSBUF_DEPTH (16)
#define CONFIG_XILINX_MCH_EMC_0_MCH2_RDDATABUF_DEPTH (16)
#define CONFIG_XILINX_MCH_EMC_0_MCH3_PROTOCOL (0)
#define CONFIG_XILINX_MCH_EMC_0_MCH3_ACCESSBUF_DEPTH (16)
#define CONFIG_XILINX_MCH_EMC_0_MCH3_RDDATABUF_DEPTH (16)
#define CONFIG_XILINX_MCH_EMC_0_XCL0_LINESIZE (4)
#define CONFIG_XILINX_MCH_EMC_0_XCL0_WRITEXFER (1)
#define CONFIG_XILINX_MCH_EMC_0_XCL1_LINESIZE (4)
#define CONFIG_XILINX_MCH_EMC_0_XCL1_WRITEXFER (1)
#define CONFIG_XILINX_MCH_EMC_0_XCL2_LINESIZE (4)
#define CONFIG_XILINX_MCH_EMC_0_XCL2_WRITEXFER (1)
#define CONFIG_XILINX_MCH_EMC_0_XCL3_LINESIZE (4)
#define CONFIG_XILINX_MCH_EMC_0_XCL3_WRITEXFER (1)
#define CONFIG_XILINX_MCH_EMC_0_INSTANCE "FLASH"
#define CONFIG_XILINX_MCH_EMC_0_HW_VER "2.00.a"

/* Definitions for TIMER_0 */
#define CONFIG_XILINX_TIMER_0_INSTANCE "xps_timer_1"
#define CONFIG_XILINX_TIMER_0_FAMILY "spartan3a"
#define CONFIG_XILINX_TIMER_0_COUNT_WIDTH (32)
#define CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY (1)
#define CONFIG_XILINX_TIMER_0_TRIG0_ASSERT (1)
#define CONFIG_XILINX_TIMER_0_TRIG1_ASSERT (1)
#define CONFIG_XILINX_TIMER_0_GEN0_ASSERT (1)
#define CONFIG_XILINX_TIMER_0_GEN1_ASSERT (1)
#define CONFIG_XILINX_TIMER_0_BASEADDR (0x83C00000)
#define CONFIG_XILINX_TIMER_0_HIGHADDR (0x83C0FFFF)
#define CONFIG_XILINX_TIMER_0_SPLB_AWIDTH (32)
#define CONFIG_XILINX_TIMER_0_SPLB_DWIDTH (32)
#define CONFIG_XILINX_TIMER_0_SPLB_P2P (0)
#define CONFIG_XILINX_TIMER_0_SPLB_MID_WIDTH (1)
#define CONFIG_XILINX_TIMER_0_SPLB_NUM_MASTERS (2)
#define CONFIG_XILINX_TIMER_0_SPLB_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_TIMER_0_SPLB_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_TIMER_0_INSTANCE "xps_timer_1"
#define CONFIG_XILINX_TIMER_0_HW_VER "1.00.a"
#define CONFIG_XILINX_TIMER_0_IRQ (0)

/* Definitions for INTC_0 */
#define CONFIG_XILINX_INTC_0_INSTANCE "xps_intc_0"
#define CONFIG_XILINX_INTC_0_FAMILY "spartan3a"
#define CONFIG_XILINX_INTC_0_BASEADDR (0x81800000)
#define CONFIG_XILINX_INTC_0_HIGHADDR (0x8180FFFF)
#define CONFIG_XILINX_INTC_0_SPLB_AWIDTH (32)
#define CONFIG_XILINX_INTC_0_SPLB_DWIDTH (32)
#define CONFIG_XILINX_INTC_0_SPLB_P2P (0)
#define CONFIG_XILINX_INTC_0_SPLB_NUM_MASTERS (2)
#define CONFIG_XILINX_INTC_0_SPLB_MID_WIDTH (1)
#define CONFIG_XILINX_INTC_0_SPLB_NATIVE_DWIDTH (32)
#define CONFIG_XILINX_INTC_0_SPLB_SUPPORT_BURSTS (0)
#define CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS (3)
#define CONFIG_XILINX_INTC_0_KIND_OF_INTR (0x00000006)
#define CONFIG_XILINX_INTC_0_KIND_OF_EDGE (0x00000006)
#define CONFIG_XILINX_INTC_0_KIND_OF_LVL (0x00000001)
#define CONFIG_XILINX_INTC_0_HAS_IPR (1)
#define CONFIG_XILINX_INTC_0_HAS_SIE (1)
#define CONFIG_XILINX_INTC_0_HAS_CIE (1)
#define CONFIG_XILINX_INTC_0_HAS_IVR (1)
#define CONFIG_XILINX_INTC_0_IRQ_ACTIVE (1)
#define CONFIG_XILINX_INTC_0_INSTANCE "xps_intc_0"
#define CONFIG_XILINX_INTC_0_HW_VER "1.00.a"

/* Peripheral counts */
#define CONFIG_XILINX_MCH_EMC_NUM_INSTANCES (1)
#define CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES (2)
#define CONFIG_XILINX_TIMER_NUM_INSTANCES (1)
#define CONFIG_XILINX_MPMC_NUM_INSTANCES (1)
#define CONFIG_XILINX_ETHERNETLITE_NUM_INSTANCES (1)
#define CONFIG_XILINX_INTC_NUM_INSTANCES (1)
#define CONFIG_XILINX_MDM_NUM_INSTANCES (1)
#define CONFIG_XILINX_UARTLITE_NUM_INSTANCES (1)
#define CONFIG_XILINX_BRAM_IF_CNTLR_NUM_INSTANCES (1)
#define CONFIG_XILINX_GPIO_NUM_INSTANCES (1)

